It should be around 158dbfs hz to get around 82dbfs snr.
Adc nose floor.
The noise floor of a measurement system is also limited by the resolution of the adc system.
For a large level analog input signal closer to full scale the adc noise floor level increases mainly due to clock jitter.
For example the noise floor of a 16 bit measurement system can never be better than 96db and for a 24 bit system the lower limit is limited to 144 db.
The noise floor level on fft plot can vary over fft size.
The ratio of the signal to noise level is defined as the signal to noise ratio snr.
Noise floor is a frequency spectrum parameter that is widely used in adc testing although it has not been properly defined and described by a formula in any adc standards yet.
For a large level analog input signal closer to full scale the adc noise floor level increases mainly due to clock jitter.
But on your measurement it is about 144dbfs for noise density and 68dbfs for snr so about 14db worse.
Noise floor is a frequency spectrum parameter that is widely used in adc testing although it has not been properly defined and described by a formula in any adc standards yet.
Using the same calculations the dynamic range of a 24 bit adc is 144db.
So it is suggested to check the noise density noise hz rather than noise floor in dbfs.
Note that the theoretical noise floor of the fft is equal to the theoretical snr plus the fft process gain 10 log m 2.
The acceptable level of adc noise power in any particular application is calculated for the case when both a 3djhri.
Ieee std 12412000 provides a formula for noise floor computation depending on the number of adc bits.
Figure 2 shows an fft output for an ideal 12 bit adc using the analog devices adisimadc program.
Ieee std 1057 1994 does not mention the noise floor but it generally uses noise or noise level that is not defined.